What actually drives PCB layout cost: six technical factors
Board area is the worst predictor of layout effort. Density, pitch, layer count, interface speed, outline geometry and schedule decide the hours. Here is how each one shows up in a quote, and how to tell whether a price is high because the board is hard or because the estimate is padded.
Density
Pitch and package type decide the escape routing
Pin count is a rough measure of work; pitch is the measure that matters. At 1.0 mm pitch a BGA escapes on through-vias with a dog-bone fanout and the routing channel is generous. At 0.5 mm there is no room for a via between pads, so the escape moves to via-in-pad or a micro-dog-bone, the trace geometry drops to 3/3 mil or finer, and the board needs an HDI build.
At 0.4 mm pitch and below, the fanout needs dedicated breakout layers and a stackup with sequential lamination. Placement and escape on a part like that can take as long as routing the rest of the board, which is why pin density is priced above the tier inclusion rather than folded into a per-pin average.
| Pitch | Escape architecture | Geometry | Effort profile |
|---|---|---|---|
| 1.0 to 0.8 mm BGA | Through-via, dog-bone fanout | 4/4 mil | Predictable; routing dominates |
| 0.65 mm BGA | Blind microvia, 1+N+1 | 3.5/3.5 mil | Constrained channels; inner-layer breakout needed |
| 0.5 to 0.4 mm BGA / WLCSP | Via-in-pad, stacked or staggered microvias | 2.5/2.5 mil | Escape work can exceed routing work |
| More than 1,500 pins | Deep microvia arrays | Design-specific | Topology planning to avoid routing dead ends |
Stackup
Layer count is a step, not a slope
Going from six to eight layers adds routing space, but it also adds two reference planes to define, dielectric symmetry to balance against warpage, and a new set of layer-transition return paths to check. Above twelve layers the stackup becomes a fabrication negotiation: core tolerances, resin starvation around heavy copper, and impedance that has to hold across varying dielectric heights.
Past sixteen layers, via aspect ratio and backdrill enter the design. Each of those is a decision with a fabrication cost and a verification cost, and both land on the layout schedule before a single net is routed.
Interfaces
Constraint volume is the hidden multiplier
A low-speed board with 800 nets and no controlled impedance routes to connectivity. The same 800 nets with DDR5, PCIe Gen 5 and two 112G lanes route to a constraint set: match groups, impedance targets, pair-to-pair spacing, stitching via rules and layer-transition limits. The copper is the same; the decision-making is not.
Serpentine tuning consumes inner-layer area, and the tuning geometry has to avoid coupling into itself. Differential pairs need intra-pair matching before they reach a BGA or connector. Every layer change needs a return via. None of that is optional on a channel with a few decibels of margin, and all of it is engineering time.
- Length and skew windows per match group, loaded as constraints rather than applied by eye.
- Ground stitching at every layer transition, with symmetric vias on differential pairs.
- Reference-plane voids under AC coupling pads and other wide launch geometries.
- Glass-weave skew handling: angled routing or spread-glass laminate where the channel needs it.
Geometry and schedule
Outline complexity and compressed timelines
A rectangular board is the easy case. Cutouts, curved edges, rigid-flex transitions and connectors on more than one edge mean pours have to be shaped, keepouts have to be honoured and every trace around the boundary is a manual decision. That is why a non-rectangular outline carries a published surcharge rather than an apologetic line item.
Schedule compression is the last multiplier and the one most often underestimated. A four-week layout delivered in ten days does not take 40 percent less work; it takes a resequenced plan, and possibly a second engineer working a parallel partition with the review gates tightened. The premium pays for capacity, and it is stated as a multiplier so you can decide whether the date is worth it.
Model the trade yourself with the Layout cost estimator, or read the published rates on the published layout pricing page.
FAQ
Common questions
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