Online PCB design tools: impedance, DDR timing, via stubs and stackup
Five calculators that answer questions you hit before routing: what width gives 50 ohms on this stackup, how much length mismatch a DDR5 byte lane can spend, where a via stub resonates, which layer assignments keep the stackup symmetric, and what the board will cost.
The short answer
Every tool runs in the browser with no login. Each one shows the equation it uses, states the range where the model holds, and flags inputs outside it rather than returning a confident number that does not apply. The results are planning values: good enough to set constraints and check a design review, not a substitute for field-solver extraction on a channel with no margin.
Calculator
The five calculators
Start with the stackup if it is still open, then impedance, then timing. The cost estimator works from counts alone and will suggest a layer count when the stackup is undecided.
Free, no account. The engineer reviews the inputs before a fixed quote is issued.
Method
Closed-form models, with the assumptions shown
A calculator that hides its model is a calculator you cannot check. If a tool returns 52 ohms and will not tell you which formulation produced it, you have no way to know whether the answer holds for your geometry or your laminate.
Each tool here names its model — Hammerstad-Jensen for microstrip, Cohn for stripline, the quarter-wave stub relation for via resonance — renders the equation, and lists the range where the closed form is reliable. Outside that range it warns instead of guessing.
- The equation, rendered, with each variable defined and its units stated.
- A stated validity range, with a warning when an input leaves it.
- Manufacturing sensitivity: Dk tolerance, etch undercut and dielectric press variation shown as a range rather than a point.
- Input validation that rejects non-physical geometry before it produces a number.
Workflow
The order the decisions actually happen in
These calculations depend on each other, and doing them out of order means redoing them. The stackup fixes the dielectric heights; the heights fix the widths and gaps for a target impedance; the geometry fixes the propagation delay; the delay fixes the length windows. Then the counts fix the price.
- Stackup planner: layer roles, dielectric heights and symmetry, with a check on the build.
- Impedance calculator: single-ended and differential width and gap for a target, with the delay per unit length.
- DDR length matching: timing allowance to length windows per match group, minus the fixed terms.
- Via stub calculator: quarter-wave null for a stub length, and the backdrill depth that moves it out of band.
- Layout cost estimator: fixed fee from counts, with every deviation itemized.
No stackup yet? The Layout cost estimator will suggest a starting layer count from the component and pin counts, which you can then model properly in the Stackup planner.
Limits
What these models will not tell you
These are two-dimensional closed forms. They model a uniform cross-section and a first-order stub resonance, which covers most of the decisions made before routing. They do not model connector launches, package parasitics, glass-weave skew or a plane cavity resonance.
When the channel has real margin, that difference does not matter. When it does not — 32 GT/s links, long backplane runs, unusual stackups — the closed form gives you a starting geometry that then has to be extracted. That work is on our high-speed PCB layout service, SI/PI verification service, backplane and high-layer layout service and DFM/DFA layout service pages.
FAQ
Common questions
Want this worked through on your board?
Send the stackup and interface list and we will check the tool result against a real layout — before the quote is fixed, not after.