Do the guides apply to Altium, Allegro or Xpedition?

Yes. Transmission-line behaviour, return current, via stubs and stackup symmetry do not depend on the CAD package. The workflow notes mention Altium because that is what we deliver in, but the rules transfer to any constraint manager.

How do the guides relate to the services?

They describe the rules the services apply. If a guide says a stub must be backdrilled to 0.15 mm, that is what happens on a board we route, and the fabrication note records it. The service pages state the scope; the guides state the engineering behind it.

Can we use these rules in our own design guide?

Yes, with attribution. Teams cite the stackup rules, handoff checklist and review sequence in internal design manuals and vendor statements of work. If you want a rule adapted to your stackup or your fabricator's process, ask and we will tell you which assumptions change.

Engineering library

PCB layout guides: high-speed routing, CAM handoff and layout economics

Thirteen guides written by the engineer who routes the boards. Six on high-speed physics and fabrication, four on the handoff and the contract, three on what layout costs and how the price is built.

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The short answer

Each guide answers one question you can act on: how long a DDR5 byte lane may be, where a via stub resonates, what a fabricator actually does with a Gerber set, which clauses give you the layout database, or why a fixed fee differs from an hourly estimate. Rules are stated as rules, with the assumption behind each one named.

Guide library

Guide directory

Start with the interface you are routing or the decision you are making. Every technical guide links to the calculator that models it and the service page that delivers it.

CommercialLayout costThe real cost structure, with the published floors and rates.Read the guide CommercialCost driversSix inputs, six kinds of work, and where the price steps.Read the guide Data handoffGerber vs ODB++What each format carries and what your fab actually imports.Read the guide CommercialOffshore vs USThe tradeoffs that show up after the quote, not before it.Read the guide High speedDDR5 layoutSmaller UI, tighter skew, new power delivery: what changes on the board.Read the guide High speedPCIe Gen 5A practical stackup and via strategy for 32 GT/s channels.Read the guide High speedWhen to backdrillUse the stub null, not habit, to decide whether to backdrill.Read the guide FabricationHDI microviasThe microvia rules that decide whether the build yields.Read the guide High speedReturn pathsThe defect a clearance check cannot see, and how to find it.Read the guide ProcessReview a layoutA review that catches what a visual pass misses.Read the guide ProcessWhat to sendThe handoff package that prevents a week of rework.Read the guide CommercialNDA & IPProtect the design before the first file leaves your network.Read the guide VerificationSI/PI or DRCWhen DRC is enough, and when the channel needs extraction.Read the guide

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Free to read. No account, no download, no email gate.

Signal and power integrity

High-speed routing and timing budgets

Once rise times drop below about 100 ps or a lane passes 5 Gbps, a trace stops behaving like a connection and starts behaving like a transmission line. The guides in this group cover the failure mechanisms that a rule check will not catch: return current detouring around a plane split, a via stub resonating inside the band, glass-weave skew in a differential pair, and a DDR5 lane whose budget was spent on package skew before routing began.

DDR5 subchannels, CA and DQ match groups, and how to build a skew budget that leaves something for the router.
PCIe Gen 5 at 32 GT/s: the 85-ohm stackup, laminate selection, backdrill depths and the AC-cap launch.
Via stub resonance, quarter-wave nulls and controlled-depth backdrilling, including when not to backdrill.
HDI microvia aspect ratio, capture-pad geometry, fill and stagger pitch at 0.4 mm pitch.
Return-path discontinuities: how to audit them, and how stitching vias and capacitors repair them.

Model the geometry as you read: the Impedance calculator, DDR length matching and Via stub resonance calculators use the same equations these guides quote.

Manufacturing and CAM

Fabrication data, DFM and the handoff

A layout is finished when the fabricator can build it without asking a question. That means a data format that carries design intent, a fabrication note that states the stackup and the exceptions, and a read-back of the package before it is sent. Most fabrication holds trace back to a handoff that was assumed rather than checked.

Gerber X2, ODB++ and IPC-2581: what each carries and what the fab still has to guess.
The four handoff errors that cost a build, from unit mismatches to stale drill data.
What to send a layout engineer on day one, and the cost of leaving each item out.
DFM and DFA rules applied during routing rather than audited at the end.

The rules are applied on our DFM/DFA layout service engagements; the release-package contents are on the high-speed PCB layout service page.

Commercial and legal

Cost, contracts and sourcing

Layout is bought as well as engineered. A quote that omits the library review is not cheaper, it is later; a contract without a present assignment leaves the copyright with the contractor; and an offshore comparison that uses the hourly rate as the whole cost usually ends with a respin. These guides are the commercial counterpart to the technical ones.

The published price tiers, the per-unit overage rates and the worked example behind a fixed fee.
The six technical cost drivers: pitch, layer count, constraint volume, outline geometry and schedule.
Onshore versus offshore, priced at total cost including iteration latency and respin risk.
NDA and IP: present assignment under 17 U.S.C. § 101, trade secret covenants and export control.
Reviewing an outsourced layout before it goes to fabrication.

Price an exact board with the Layout cost estimator, read the published layout pricing, or open the Master Services Agreement.

FAQ

Common questions

The engineer who runs the layout engagements. Numbers are taken from IPC and JEDEC where a standard exists, from controller and fabricator documentation where a vendor limit exists, and from our own stackups where neither does. Where a figure is a planning default rather than a specification, the guide says so.

Keep going

Layout cost estimator Stackup planner DDR length matching Via stub resonance published layout pricing high-speed PCB layout service

Have a board that needs more than a guide?

Send the stackup, the interface list and the target date. We will confirm the scope and price the layout as a fixed fee.

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