PCIe Gen 5 layout: 32 GT/s on a board that has to pass compliance
Gen 5 doubles the bit rate to 32 GT/s and leaves the channel budget roughly the same, which means the loss has to come out of the board. Most of the work is material choice, via stubs and the launch geometry at the connector and the AC coupling caps — not the straight run in the middle.
Channel budget
Where 32 GT/s leaves you
PCIe Gen 5 runs at 32 GT/s per lane with NRZ signaling, so the Nyquist frequency is 16 GHz. The specification's loss budget at that frequency is around -36 dB end to end including the package, the connector and the board. A long FR-4 run eats that on its own, which is why the laminate choice is a Gen 5 decision and not a procurement detail.
Do the arithmetic before placement: controller package loss, board loss per inch at 16 GHz for the candidate laminate, connector loss, and the allowance for two AC coupling capacitors. If the sum lands close to the budget with nothing left, the design has no margin for the via transitions it will actually need.
| Element | What drives it | Layout leverage |
|---|---|---|
| Controller package | Silicon and package design | None — it is a fixed deduction |
| Board trace | Laminate Df, copper roughness, length | High: material, length, layer choice |
| Connector | Connector family and pin assignment | Moderate: family choice, launch geometry |
| Via transitions | Stub length, antipad, backdrill | High: layer assignment and backdrill depth |
| AC coupling caps | Package size, pad geometry, voiding | Moderate: 0201 parts, ground void under pads |
Stackup
85 ohms, and a laminate that can hold it
PCI-SIG specifies 85 ohms differential for Gen 5, not the 100 ohms that older designs inherited. At 85 ohms the traces are wider for a given dielectric height, which lowers insertion loss and crosstalk and matches the termination inside the transceiver. Do not carry a 100-ohm rule forward from a Gen 3 design.
At 16 GHz the skin depth in copper is about 0.5 µm, so current is travelling in the surface profile of the foil. Standard electrodeposited copper with 5 to 8 µm Rz adds conductor loss that no amount of routing skill recovers. Specify HVLP foil with Rz at or below 1.5 µm, and get the fabricator to confirm it is in stock before the stackup is frozen.
Physical detail
Stubs, backdrill and the AC cap launch
A through-via on a 2.4 mm board leaves a stub that resonates well inside the Gen 5 band. Backdrill every signal via on the lane to a residual stub of 0.15 mm or less, or move the layer transition into an HDI build with blind microvias. Then check the antipad: the backdrill tool is larger than the drill, and an antipad sized for the original hole gets sliced.
AC coupling capacitors are the other common failure. An 0201 cap on wide pads looks capacitive at 16 GHz: impedance drops through the pad and the transition reflects. Remove the reference plane directly under the pads on the layer below, keep the pair spacing through the launch, and place the caps in line with the pair rather than on stubs.
Connector launches deserve the same treatment. Follow the connector vendor's footprint and breakout exactly, including the ground via pattern; the footprint is part of the channel model, and a tidier-looking breakout that ignores it usually measures worse.
Model the launch before you commit to it with the Impedance calculator, check the stub resonance with the Via stub resonance, and see the extraction scope on the SI/PI verification service page.
FAQ
Common questions
Want this worked through on your board?
Send the stackup and interface list and we will check the PCIe Gen 5 channel against a real layout — before the quote is fixed, not after.