Why is 50 Ω the usual single-ended target?

It is a compromise, not a physical constant. It is close to the impedance that maximises power handling for an air line, close to the loss minimum for many PCB geometries, and it became the standard test and connector impedance. Interfaces specify their own numbers — 100 Ω differential for Ethernet and PCIe, 90 Ω for some USB and DDR variants — and those specifications win over the convention.

Is a 100 Ω differential pair just two 50 Ω traces?

Only when the traces are far enough apart to be effectively uncoupled. Close traces share field, so the differential impedance is lower than 2·Z0. The calculator solves the single-ended width first and then the gap for the differential target, which is the order that keeps both the odd-mode and common-mode impedances sane.

Why does my fabricator's impedance come out different from this calculator?

The most common reasons are the laminate's Dk at the actual frequency, the soldermask over the trace, copper thickness after plating, and the fab's own field solver or test coupon. The closed forms on this page are design-entry models; the fab builds a coupon and adjusts the width. Use the tolerance window to see how much of the difference is normal process variation.

How accurate are the microstrip and stripline models?

The microstrip form is quoted at about 1% for 0.1 ≤ w/h ≤ 10 with 1 ≤ εr ≤ 15 and t ≤ 0.2h. The stripline fit is quoted for 0.075 ≤ w/b ≤ 3 with t ≤ 0.2b; expect a few percent, and more near the edges of the range. The tool warns when the geometry leaves the fitted window rather than hiding the extrapolation.

Do I need a field solver instead?

For a production high-speed channel, yes — at least once, for the stackup you will actually build. A field solver captures soldermask, copper roughness, nearby traces, asymmetric cavities and frequency-dependent Dk that these closed forms do not. The calculator is for making the first fifty decisions quickly; the solver is for signing the channel off.

Free tool · Transmission lines

Impedance target calculator: solve width, gap and tolerance

Solve microstrip and stripline impedance from a real stackup, invert it for the trace width or differential gap, and see the worst-case window a fabricator's tolerances will produce.

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The short answer

Characteristic impedance is the ratio of voltage to current for a wave travelling along the line, set by the trace geometry and the dielectric around it — not by the copper's resistance. A 50 Ω microstrip on 0.2 mm FR-4 is roughly 0.38 mm wide with 1 oz copper; a 50 Ω stripline between 0.5 mm planes is roughly 0.26 mm wide. Use the solver below for your own stackup, then design to the tolerance window rather than the nominal number.

Calculator

Microstrip and stripline impedance calculator

Choose the line type, enter the stackup, and the tool solves both directions: geometry to impedance and target impedance back to width and gap. The tolerance panel re-evaluates the model at every corner, and the loss panel shows why a line that is impedance-correct can still be too lossy.

Line type

Units

Laminate Dk

From the laminate datasheet at your frequency.

Dielectric height (h)mm

Trace to reference plane.

Trace width (w)mm

Copper thickness (t)mm

1 oz ≈ 0.035 mm finished.

Targets and frequency

Target Z0Ω

Target ZdiffΩ

Edge-to-edge gap (s)mm

FrequencyGHz

Loss tangent (Df)

0.02 for ordinary FR-4; lower for high-speed laminates.

Manufacturing tolerance box

Width± %

Dielectric height± %

Dk± %

Copper thickness± %

Impedance and transmission-line properties

Nominal values at the frequency you entered, from the shared closed-form model.

Solved

Single-ended: 47.86Ω
Differential: 78.13Ω
Effective Dk: 3.288
Delay: 6.049ps/mm
Wavelength: 165.33mm
Dielectric loss: 0.058dB/in
Conductor loss: 0.050dB/in
Tolerance window: 41.4–55.0Ω
Width sensitivity: -70.6Ω/mm

Impedance across a ±30% width sweep. The dashed line is the target; the vertical line is the width you entered.

Solve for the target

Two inversions of the same model: the width that hits the single-ended target, then the gap that hits the differential target at that width.

Width for 50 Ω

0.351 mm

Achieves 50.00 Ω. Bisection on the monotonic impedance curve.

Gap for 90 Ω differential

0.327 mm

At the solved width, achieves 90.00 Ω. Edge-coupled fit (IPC-style).

Where the model stops

The microstrip form is Hammerstad–Jensen with Wheeler's thickness correction; the stripline form is Cohn's synthesis. Both are quasi-static: soldermask, copper roughness, nearby traces and frequency-dependent Dk are not included. The tolerance window evaluates every corner of the box you enter, not a linear error bar. For a production channel, extract the actual stackup.

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Free, no account. The engineer reviews the inputs before a fixed quote is issued.

Want the derivation? Jump to the math behind the calculator.

The math

The formulas, with the working shown

Each equation is rendered as MathML, explained in plain language, and shown as LaTeX source you can copy. The variable list says what every symbol means; the model-limit note says where the formula stops being trustworthy.

Microstrip characteristic impedance

Z_{0} = \frac{η_{0}}{2 π \sqrt{ε_{e f f}}} \ln (\frac{F_{1} h}{w} + \sqrt{1 + {(\frac{2 h}{w})}^{2}}) F_{1} = 6 + (2 π - 6) \exp [- {(\frac{30.666 h}{w})}^{0.7528}]

Hammerstad and Jensen's closed form for a microstrip line. The logarithm captures the field spreading into the air above the trace; F1 is the fit that keeps the formula accurate from narrow to wide strips.

η0: free-space wave impedance, 376.73 Ω
h: dielectric height from trace to reference plane
w: effective trace width (drawn width plus the copper-thickness correction)
ε_eff: effective relative permittivity from the next block

The prefactor sets the scale: η0 is the impedance of free space (about 376.7 Ω), and dividing by √εeff slows the wave and lowers the impedance as the dielectric loads the line.

The argument of the logarithm grows as the trace gets narrower (h/w grows), which raises the impedance. A wide trace has a small h/w and a low impedance. The square-root term is the fringing field at the trace edges.

F1 is not a correction fudge: it is the published fit that makes the expression accurate for both narrow and wide strips without a separate piecewise formula.

Model limit: The same form is used in `impedance.ts` for the calculator, the stackup planner and the DDR delay model, so the three tools cannot disagree.

LaTeX source

Z_0 = \frac{\eta_0}{2\pi\sqrt{\varepsilon_{eff}}}\ln\left(\frac{F_1 h}{w}+\sqrt{1+\left(\frac{2h}{w}\right)^2}\right) \quad F_1 = 6+(2\pi-6)\exp\left[-\left(\frac{30.666h}{w}\right)^{0.7528}\right]

Microstrip effective permittivity

ε_{e f f} = \frac{ε_{r} + 1}{2} + \frac{ε_{r} - 1}{2} {(1 + \frac{10 h}{w})}^{- a b}

The effective Dk of a microstrip line is a weighted average of air and laminate. Wider traces and thinner dielectrics push the field into the laminate and raise εeff.

ε_r: laminate relative permittivity
a, b: empirical exponents from the Hammerstad–Jensen fit
h, w: dielectric height and trace width

The limiting cases make the equation easy to remember: an infinitely narrow trace has εeff = (εr + 1)/2, the arithmetic mean of air and laminate; an infinitely wide one approaches εr.

The exponents a and b are the Hammerstad–Jensen fits, given on the DDR page and implemented once in `impedance.ts`. They depend on w/h and εr, not on frequency.

Stripline needs no equivalent equation: the field never leaves the laminate, so εeff = εr. That single fact explains why inner-layer traces are slower.

Model limit: Quasi-static: the model does not include dispersion, soldermask or a nearby trace.

LaTeX source

\varepsilon_{eff} = \frac{\varepsilon_r+1}{2} + \frac{\varepsilon_r-1}{2}\left(1+\frac{10h}{w}\right)^{-ab}

Stripline characteristic impedance

Z_{0} = \frac{30 π}{\sqrt{ε_{r}} (x + 0.441)} x = \frac{w}{b} if \frac{w}{b} \geq 0.3444 x = 0.6 - {(0.85 - \frac{w}{b})}^{2} otherwise

Cohn's conformal-mapping fit for a symmetric stripline, with b the dielectric thickness between the two planes. The two branches keep the fit accurate from narrow to wide strips.

b: dielectric thickness between the two ground planes
w: effective strip width
x: the fitted width term, piecewise in w/b

A stripline has two reference planes, so for the same dielectric spacing it is roughly half the impedance of a microstrip and needs a narrower trace to reach 50 Ω. That is why inner-layer routing is denser but harder to manufacture.

The constant 0.441 is the fringing correction: without it the formula would be the pure parallel-plate result 30π/(√εr · w/b), which overestimates impedance for practical widths.

At w/b = 0.3444 the two branches meet at Z0 = 120/√εr, which is the boundary quoted in the source. Beyond the fitted range the tool warns rather than pretending the number is exact.

Model limit: Fitted for 0.075 ≤ w/b ≤ 3 with t ≤ 0.2b. An asymmetric stackup needs the capacitance-combination method used by the planner.

LaTeX source

Z_0 = \frac{30\pi}{\sqrt{\varepsilon_r}\left(x+0.441\right)} \quad x = \frac{w}{b}\ \text{ if }\ \frac{w}{b}\ge 0.3444 \quad x = 0.6-\left(0.85-\frac{w}{b}\right)^2\ \text{ otherwise}

Edge-coupled differential microstrip

Z_{d i f f} = 2 Z_{0} (1 - 0.48 e^{- 0.96 s / h})

The pair impedance starts at twice the single-ended value and falls as the gap closes, because each trace's field is partially cancelled by the other's.

Z0: single-ended impedance of one trace in the pair
s: edge-to-edge gap between the traces
h: dielectric height under the traces

The exponential term is the coupling: at s/h = 0 it is 0.48, so Zdiff is 1.04·Z0 — far below 2·Z0. As s/h grows, the exponential decays and the pair approaches two independent 50 Ω lines.

This is why a 100 Ω differential pair on FR-4 is not two 50 Ω traces pushed together: it needs a narrower trace or a larger gap than the naive 2:1 assumption suggests.

The fit is reasonable for s/h ≥ 0.2. Tighter gaps need a field solver because the odd-mode field is no longer a perturbation of the single-ended one.

Model limit: Edge-coupled only. Broadside-coupled or asymmetric pairs use a different geometry and should be extracted.

LaTeX source

Z_{diff} = 2Z_0\left(1-0.48\,e^{-0.96s/h}\right)

Edge-coupled differential stripline

Z_{d i f f} = 2 Z_{0} (1 - 0.347 e^{- 2.9 s / b})

The inner-layer counterpart. Coupling decays faster with spacing than in microstrip because the field is fully confined to the laminate, so the pair reaches its uncoupled limit at a smaller gap.

b: plane-to-plane dielectric thickness
s: edge-to-edge gap
Z0: single-ended impedance of one trace

The coefficient (2.9 rather than 0.96) is the practical difference between the two environments: stripline fields are contained, so the traces stop seeing each other sooner.

The reference length b is the dielectric between the two ground planes, not the distance from the trace to one plane. Mixing the two is a common way to get a differential impedance that looks right and a single-ended impedance that does not.

As with microstrip, solve width first and gap second; the single-ended target still has to be met for the pair to have the right common-mode impedance.

Model limit: Fitted for moderate coupling; extract tight pairs or asymmetric stacks.

LaTeX source

Z_{diff} = 2Z_0\left(1-0.347\,e^{-2.9s/b}\right)

Dielectric attenuation

α_{d} = \frac{π f}{c_{0}} \sqrt{ε_{e f f}} \tan δ α_{d} [\frac{dB}{m}] = 8.686 α_{d} [\frac{Np}{m}]

Loss in the laminate grows linearly with frequency and with the loss tangent. It does not depend on the trace width, which is why widening a trace fixes conductor loss but not dielectric loss.

f: frequency
tanδ: loss tangent (Df) of the laminate at that frequency
α_d: dielectric attenuation

The factor πf/c0 is the phase constant of the wave; multiplying by tanδ turns the stored energy into heat. The square root of εeff is the same slow-down factor that sets delay.

Nepers and decibels differ by 8.686. The calculator shows dB per inch because that is how channel loss is usually quoted, and the conversion is done once in `impedance.ts`.

For microstrip the page scales the result by the filling factor q = (εeff − 1)/(εr − 1), because part of the field is in air and does not see the laminate loss.

Model limit: The conductor term in the calculator counts only the strip, so it is a lower bound; surface roughness and the return plane add loss.

LaTeX source

\alpha_d = \frac{\pi f}{c_0}\sqrt{\varepsilon_{eff}}\tan\delta \quad\quad \alpha_d\left[\frac{\text{dB}}{\text{m}}\right] = 8.686\,\alpha_d\left[\frac{\text{Np}}{\text{m}}\right]

The worst-case impedance window

Z_{0}^{\min} = \min_{corners} Z_{0} (w \pm Δ w, h \pm Δ h, ε_{r} \pm Δ ε_{r}, t \pm Δ t)

The tolerance window is not a linear error bar. The model is evaluated at every corner of the manufacturing box and the minimum and maximum are reported, because the impedance surface is curved.

Δw, Δh, Δε_r, Δt: the manufacturing tolerances for width, height, Dk and copper thickness
Z0^min: the lowest impedance anywhere in the tolerance box

Width and height pull in opposite directions: wider copper lowers impedance, a taller dielectric raises it. A fab that etches narrow and laminates thick can therefore land far from nominal even when each tolerance is individually acceptable.

A linearised sensitivity (dZ/dw) is useful for intuition but understates the corner case when several tolerances move together. This tool evaluates the corners instead.

If the spread is unacceptable, the lever with the most authority is usually the dielectric height. It is set by the stackup and the prepreg, not by the router.

Model limit: The window assumes the tolerances are independent. Correlated process shifts (a whole panel etched narrow) can move the entire box.

LaTeX source

Z_0^{\min} = \min_{\text{corners}} Z_0\left(w\pm\Delta w,\ h\pm\Delta h,\ \varepsilon_r\pm\Delta\varepsilon_r,\ t\pm\Delta t\right)

Theory

Characteristic impedance, and the half of the circuit people forget

Characteristic impedance is the ratio of voltage to current in a wave travelling along the line. It comes from the cross-section — trace width, dielectric height, dielectric constant — not from the copper's resistance, and not from the trace's length. Change the reference spacing and the impedance moves even if the trace does not.

The return current is the other half of the transmission line. In microstrip it crowds into the plane directly beneath the trace; in symmetric stripline it divides between the two planes. Interrupt either plane and the local inductance changes, which appears as an impedance discontinuity that no amount of width tuning will remove.

On interfaces such as PCIe Gen 5, DDR5 and USB4, our high-speed PCB layout service page covers the stackup targets and routing rules that come out of this.

Z₀ belongs to the whole cross-section, plane included — a trace cannot have an impedance without its reference.
Differential impedance is not twice the single-ended value: pair coupling pulls it down as the gap closes.
The same width produces a different impedance on each layer because the dielectric height differs.
A TDR shows the impedance profile along the line; a DRC check only sees geometry.

Tolerance

Why the nominal result is not the number you get back

A solved value of 50.0 Ω is a CAD number. Etching undercuts the top of the trace by roughly 0.5 to 1 mil, lamination moves prepreg thickness by around ±10 percent, and dielectric constant drifts about ±5 percent with resin content. The board you receive sits somewhere inside that envelope.

The tolerance panel re-solves at the corners and reports the minimum, nominal and maximum. If the interface needs ±7 percent and the design only holds ±10 percent, the answer is a tighter dielectric spec or a different geometry — decided before the artwork is released, not after the impedance coupon comes back.

The solver covers the width, dielectric-thickness and Dk corners. The Stackup planner shows how the same dielectric allocation drives widths on every signal layer at once.

Differential pairs

Solving width and gap together

In a differential pair the two traces couple. The field of one reaches the other, mutual capacitance and inductance change the odd-mode impedance, and the effect decays as the edge-to-edge gap grows relative to the dielectric height. That is why a copied width from a single-ended table does not produce the differential target.

The solver runs in two stages: size the trace for the single-ended target on that layer, then iterate the gap until the differential target is met. Below a gap-to-height ratio of about 0.25 the closed form loses accuracy and the geometry needs a 2D field solve before it is trusted.

For tightly coupled structures, the SI/PI verification service page covers the field-solver extraction.

Loss

Impedance-correct is not the same as low-loss

A line can hit its impedance target exactly and still fail the channel budget. Attenuation has two components: dielectric loss, which rises linearly with frequency and tracks the laminate's dissipation factor, and conductor loss, which rises with the square root of frequency through skin depth.

By a few gigahertz the skin depth is below a micrometre, so current runs in the surface profile of the copper. Standard electrodeposited foil with 5 to 8 µm roughness adds 30 to 50 percent to conductor loss against HVLP foil. The loss panel separates the two so you can see which one is eating the budget.

For production sign-off, dielectric dispersion and copper roughness belong in a 2D or 3D extraction. The SI/PI verification service and DFM/DFA layout service pages cover that scope and the CAM verification that follows it.

FAQ

Common questions

There is no single answer, because it depends on which layers the trace uses and how the 1.6 mm is distributed. A typical 4-layer build with 0.2 mm outer dielectric and 1 oz copper lands near 0.38 mm for 50 Ω microstrip; an inner stripline between two 0.4 mm dielectrics lands near 0.2 mm. Enter the actual dielectric height and Dk in the calculator rather than copying a width from another board.

Keep going

Stackup planner DDR length matching Via stub resonance high-speed PCB layout service SI/PI verification service published layout pricing

Want this worked through on your board?

Send the stackup and interface list and we will check the impedance target against a real layout — before the quote is fixed, not after.

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