How to review a PCB layout you're outsourcing
A layout can pass every check the contractor runs and still be wrong, because the checks were configured to pass. Review the rule set before you review the routing, check the mechanical fit in 3D before you look at the artwork, and read the DRC waiver list as carefully as the board itself.
Start with the rules
Audit the constraint set, not the DRC result
A clean DRC report only means the design matches the rules that were loaded. If a clearance was relaxed, a differential pair impedance was left at the tool default, or a net class was never assigned, the report is clean and the board is not. Ask for the rule deck and the waiver list before you open the PCB.
Compare the net classes against your schematic. Check that the impedance rules match the stackup your fabricator will build, not a nominal stackup from a previous project. Every suppressed violation should have a name next to it and a reason you accept.
| Stage | What to inspect | Ask for |
|---|---|---|
| Rules | Net classes, impedance targets, clearances, waiver log | Constraint manager export and DRC waiver report |
| Mechanical | Connector mating, component heights, mounting hardware, cable bend | 3D STEP assembly checked in your mechanical CAD |
| Placement | Decoupling distance, thermal paths, analogue and digital separation | Placement review with power and ground highlighted |
| Routing | Reference continuity, length and skew reports, via strategy | Per-group skew report and return-path overlay |
| Release | Net comparison, drill, mask, paste, fabrication notes | IPC-D-356 comparison and a CAM read-back |
Placement and fit
Check the mechanical fit before the copper
Import the board's 3D STEP model into your own mechanical tool and look at it against the enclosure. Connector shells, tall electrolytics, heatsinks and screw heads cause more respins than any routing error, and they are cheap to fix at placement review.
Then look at thermal paths and decoupling. A power converter with no via array into the ground plane, or a bypass capacitor parked across the board from the pin it serves, is a layout decision that no schematic review would catch.
Routing and release
What to check in the routing and the release package
- Every high-speed net has a continuous reference plane; follow the layer transitions by hand.
- Length and skew reports are per match group and include the layer-transition delay, not raw net length.
- Via counts are symmetric within a differential pair, and backdrill depths are in the fabrication notes if they are needed.
- Test points exist where bring-up will need them, and they are not stubs hanging off a 16 GHz channel.
- The Gerber set reads back into a CAM tool with the right layer count, the right drill file and no unnamed layers.
- The BOM, the reference designators and the pick-and-place rotation match the physical parts.
Our own review gates are listed on the our onboarding process page, and the deliverables each one produces are on the high-speed PCB layout service page. To check the stackup a layout was routed against, rebuild it in the Stackup planner.
FAQ
Common questions
Want this worked through on your board?
Send the stackup and interface list and we will check the layout review against a real layout — before the quote is fixed, not after.