Why must a stackup be symmetric?

Mirroring the copper weights and dielectric heights about the centre keeps the board flat through lamination and reflow. An asymmetric build can bow or twist, which changes assembly yield and can crack vias. Symmetry also makes the mirrored layers have the same impedance, so the same trace width works on both.

Does every signal layer need an adjacent ground plane?

Ideally yes. The return current flows in the nearest plane, so a signal with no adjacent reference has an uncontrolled return path and an impedance that depends on whatever copper happens to be nearby. A signal between two different plane nets is better than one with no plane, but it needs stitching or a continuous reference under the route.

Why is the cavity resonance independent of dielectric thickness?

For a parallel-plate cavity with conducting walls, the resonant frequencies are set by the board dimensions and the Dk, not by the plate separation. Thinning the dielectric increases the capacitance and lowers the cavity's characteristic impedance, but the half-wave resonance across the board stays at the same frequency. Both effects matter, for different reasons.

Can the planner design an HDI or microvia stackup?

No. It plans symmetric through-hole stackups. HDI adds build-up layers, microvias, via-in-pad, sequential lamination and different design rules; those need a fabricator's HDI capability and a separate stackup drawing. Use this planner for the core, then hand the HDI portion to a fab's field application engineer.

How accurate are the impedance numbers in the plan?

They use the same Hammerstad–Jensen microstrip and Cohn stripline models as the impedance calculator, with the actual dielectric height each layer sees. That makes them design-entry accurate (a few percent inside the fitted ranges), but the fab's final stackup, soldermask, copper roughness and Dk at frequency will move them. The plan is a starting point for the fab drawing, not the release.

Free tool · Stackup planning

PCB layer stackup planner with legal layer steps and impedance

Plan a symmetric 2–40 layer stackup, allocate the dielectric, solve the trace width and differential gap on every signal layer, and check plane-pair capacitance and cavity modes before the fab sees the drawing.

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The short answer

A usable stackup does four things at once: it gives every signal layer a reference plane, keeps the copper and dielectric symmetric so the board does not bow, allocates dielectric heights that make the target impedances buildable, and survives the fabricator's prepreg inventory. Start with an even layer count, choose the roles, then let the planner solve the widths — and treat its output as a plan to confirm with the fab, not a release drawing.

Calculator

Layer stackup planner

Pick a legal layer count, set the finished thickness and copper weights, then adjust the dielectric profile. Every signal layer is solved against its actual reference planes; warnings appear where a target needs a width the fab cannot etch, where a signal sits between two different plane nets, or where the build is not balanced.

Copper layers

Only the published even stackups.

Finished thicknessmm

Outer copperoz

Inner copperoz

Laminate Dk

Dielectric profile

Impedance targets and fabrication rules

Single-ended targetΩ

Differential targetΩ

Minimum trace widthmm

Minimum gapmm

Board outline (for plane-pair physics)

Board widthmm

Board heightmm

Layer roles

L1 SignalL2 GroundL3 SignalL4 PowerL5 GroundL6 SignalL7 GroundL8 Signal

Stackup plan

Thickness, solved widths and the reference each signal layer actually sees.

Planned

Total thickness: 1.600mm
Copper: 0.174mm
Dielectric: 1.426mm
Signal layers: 4
Plane layers: 4
Plane pairs: 1
Narrowest trace: 0.168mm
Tightest gap: 0.151mm
Thickness error: 0.000mm

Design-review flags

Layer 3: Layer 3 sits between ground (layer 2) and power (layer 4). Route it against one reference and keep the other plane continuous, or add stitching capacitors if the two nets must be tied.

Layer-by-layer plan

Dielectric below is the gap to the next copper layer. Width and gap are solved for the target impedances on that layer's own reference height.

Stackup layers, copper and dielectric thicknesses, and solved impedance geometry.
Layer	Role	Cu mm	Dielectric below mm	Line	Width mm	Gap mm	Z0 Ω
L1	Signal	0.0348	0.2037	Microstrip	0.358	0.333	50.0
L2	Ground	0.0174	0.2037	—	—	—	—
L3	Signal	0.0174	0.2037	Stripline	0.168	0.151	51.0
L4	Power	0.0174	0.2037	—	—	—	—
L5	Ground	0.0174	0.2037	—	—	—	—
L6	Signal	0.0174	0.2037	Stripline	0.168	0.151	51.0
L7	Ground	0.0174	0.2037	—	—	—	—
L8	Signal	0.0348	—	Microstrip	0.358	0.333	50.0

The widths are solved against the target single-ended impedance; the gaps are solved for the target differential impedance at those widths. The copper-thickness correction is included.

Adjacent ground/power pairs

Parallel-plate capacitance and the first cavity modes for the board outline you entered.

Plane-pair capacitance and cavity resonances.
Pair	Dielectric mm	Capacitance pF	First mode GHz	Diagonal GHz
L4–L5	0.2037	1,495.2	0.72	1.16

The cavity modes are set by the board dimensions and Dk, not by the dielectric thickness. Thinning the core raises the capacitance without moving the first mode.

This is a plan, not a release drawing

The fabricator owns the prepreg and core inventory, the lamination cycle and the final thickness tolerance. Expect the gaps to snap to stocked materials, then re-run the widths. Microvia and HDI builds need a separate stackup drawing.

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Free, no account. The engineer reviews the inputs before a fixed quote is issued.

Want the derivation? Jump to the math behind the calculator.

The math

The formulas, with the working shown

Each equation is rendered as MathML, explained in plain language, and shown as LaTeX source you can copy. The variable list says what every symbol means; the model-limit note says where the formula stops being trustworthy.

Finished thickness

T = \sum_{k = 1}^{N} t_{Cu, k} + \sum_{i = 1}^{N - 1} d_{i}

The planner spends the target thickness on copper first and dielectric second. If the copper alone exceeds the target, no dielectric allocation can rescue the build.

T: finished board thickness
t_Cu,k: copper thickness of layer k (outer or inner weight)
d_i: dielectric thickness of gap i (between layer i and i+1)
N: copper layer count

One ounce of plated copper is nominally 34.8 µm. The planner uses that figure for every layer, with separate outer and inner weights, because outer layers are often 1 oz while inner layers are 0.5 oz.

The remaining thickness is split across N−1 dielectric gaps. An even split is the simplest starting point; the thin-outer profile is common when the outer layers need tighter impedance or better coupling, and it is still symmetric.

The planner adds the allocation back up and reports the error. It should be zero unless the copper has consumed the whole target, in which case it warns instead of producing a negative dielectric.

LaTeX source

T = \sum_{k=1}^{N} t_{\text{Cu},k} + \sum_{i=1}^{N-1} d_i

The dielectric a trace actually sees

b_{k} = d_{k - 1} + d_{k} h_{outer} = d_{1} or d_{N - 1}

An inner stripline is referenced by the nearest plane above and the nearest plane below, so its dielectric is the sum of the two gaps. An outer microstrip sees only the gap beneath it (or above it, on the bottom layer).

b_k: plane-to-plane dielectric for an inner signal on layer k
d_{k-1}: dielectric between the plane above and the signal
d_k: dielectric between the signal and the plane below

The equation assumes the signal is centred between the planes. When the gaps are unequal, the planner uses the asymmetric combination in the next block rather than pretending the trace is centred.

If the adjacent layer is another signal rather than a plane, the reference is the next plane beyond it and the dielectric includes the intervening gap. That is electrically valid only if the intervening copper does not disturb the field; the planner warns about one-sided references.

The distinction between b (plane-to-plane dielectric) and the gap to one plane is the most common source of impedance errors when a stackup is copied from a spreadsheet.

LaTeX source

b_k = d_{k-1} + d_k \quad\quad h_{\text{outer}} = d_1\ \text{or}\ d_{N-1}

Asymmetric stripline combination

Z = \frac{2 Z_{U} Z_{L}}{Z_{U} + Z_{L}}

When a trace is not centred between its planes, the two half-spaces are combined as parallel capacitances. For a centred trace the expression reduces to the symmetric impedance.

Z_U: symmetric stripline estimate for the upper half
Z_L: symmetric stripline estimate for the lower half

Each side is treated as a symmetric stripline whose plane spacing is twice the distance from the trace centre to that plane. The two capacitances add, and because Z is inversely proportional to capacitance, the combined impedance is the expression above.

If Z_U = Z_L = Z, the expression becomes 2Z²/2Z = Z, which is the symmetric case. That is the sanity check the tests pin.

The caveat is that this is still a quasi-static approximation. A strongly asymmetric cavity, a plane with a large cut-out or a trace near a board edge needs a field solve.

LaTeX source

Z = \frac{2\,Z_U\,Z_L}{Z_U+Z_L}

Plane-pair capacitance

C = ε_{0} ε_{r} \frac{A}{d}

Adjacent power and ground planes are a parallel-plate capacitor. The capacitance is set by the overlap area, the Dk and the dielectric thickness.

ε0: vacuum permittivity, 8.854 × 10⁻¹² F/m
A: overlap area of the two planes
d: dielectric thickness between the planes

ε0 is 8.854 pF/m; the planner converts the board area from mm² to m² and the dielectric from mm to m before evaluating the expression, then reports picofarads.

Doubling the area doubles the capacitance; halving the dielectric thickness also doubles it. That is why a thin core between power and ground is such an effective high-frequency decoupling capacitor.

The capacitance is only useful if the planes are connected to the devices with low inductance. The plane pair does not replace the decoupling network; it provides the high-frequency floor that the network works against.

Model limit: The formula ignores the fringing field at the board edges and any plane cut-outs, so it slightly underestimates the real capacitance.

LaTeX source

C = \varepsilon_0\,\varepsilon_r\,\frac{A}{d}

First cavity resonance

f_{m n} = \frac{c_{0}}{2 \sqrt{ε_{r}}} \sqrt{{(\frac{m}{a})}^{2} + {(\frac{n}{b})}^{2}}

A plane pair is a rectangular cavity. The lowest mode is a half wave across the longer board dimension, and the higher modes add the other dimension.

a, b: board dimensions along the two plane axes
m, n: mode indices (1,0 is the lowest)
ε_r: dielectric Dk between the planes

For the (1,0) mode the square root is simply 1/a, so f = c0/(2a√εr). With a 100 mm board and εr = 4.3, the first mode is about 0.72 GHz.

The mode frequency does not depend on the dielectric thickness. Thinning the dielectric raises the capacitance but leaves the cavity modes where they were; that is the counter-intuitive point the planner makes visible.

If a clock harmonic or a package resonance lands on a cavity mode, the PDN impedance can spike even with plenty of decoupling capacitance. Board dimensions, plane partitioning and via placement are the levers.

LaTeX source

f_{mn} = \frac{c_0}{2\sqrt{\varepsilon_r}}\sqrt{\left(\frac{m}{a}\right)^2+\left(\frac{n}{b}\right)^2}

Architecture

What a stackup decides before any routing happens

A stackup fixes four things at once: how many signals can cross each other without vias, which impedance targets are reachable, how much copper sits between a signal and its return, and how much inductance the power planes add to the PDN. Change it later and every controlled net has to be re-impedanced.

The planner assigns a role to each layer and solves each signal layer against its own reference planes. It warns when a target needs a trace narrower than the fab can etch (below 0.075 mm / 3 mil), when a signal layer sits between two different plane nets, and when the build is not balanced.

Layer roles: ground planes, power planes and impedance-controlled signal layers.
Dielectric allocation: spending the finished thickness across prepreg and core, symmetrically.
Impedance synthesis: single-ended width and differential gap on every signal layer.
Plane-pair capacitance and first cavity resonance, from the board dimensions.
DFM warnings: split references, unbalanced copper and unetchable widths.

Layer counts step in even increments from 2 to 40. The published layout pricing page shows which tiers those steps fall into.

Symmetry

Why the build has to be symmetric

A board is laminated under heat and pressure, then cools. If one half of the stack carries more copper or a different dielectric distribution than the other, the two halves shrink differently and the board bows. IPC-6012 puts the Class 3 limit at 0.75 percent bow and twist, and a balanced build is how you stay inside it.

That is why the planner works in even layer counts: mirror the copper weights and dielectric heights about the centre line and the stress cancels. An odd count with a compensating dummy layer is a conversation with the fabricator, not a checkbox.

Return paths

When a signal layer sits between two different planes

A signal layer needs an adjacent plane, and ideally the same plane on both sides. In a common eight-layer build — signal, ground, signal, power, ground, signal, ground, signal — the third layer has ground above and power below. A fast signal routed there changes its reference mid-flight unless it is stitched at every transition.

The planner flags that configuration rather than hiding it, because it is often the right stackup anyway. The fix is a careful layer assignment plus stitching capacitors at the transitions, not a different layer count.

Both the DDR length matching and Impedance calculator assume the reference plane is continuous, because neither calculation means anything if it is not.

Power distribution

Plane pairs as capacitance, and as a cavity

Adjacent ground and power planes form a parallel-plate capacitor: capacitance rises with overlap area and dielectric constant and falls with spacing. A 2 to 3 mil core between them delivers low-inductance charge above 100 MHz, which is exactly where discrete capacitors have turned inductive and stopped helping.

The same pair is also a resonant cavity. When a board dimension approaches a half wavelength at some frequency, the pair rings, the impedance spikes and the structure radiates. The tool computes the first resonance from the board dimensions so you can see where that frequency sits relative to your clock harmonics.

Mitigation is a stitching-via fence and distributed decoupling, modelled as part of a SI/PI verification service engagement.

Handoff

The plan is not the fabrication drawing

The planner produces an electrical baseline. The fabricator turns it into glass styles — 1080, 2116, 7628 — and core thicknesses from an IPC-4101 slash sheet. Resin flow during lamination then moves the cured dielectric thickness depending on the copper density around it, and the delivered impedance follows the delivered thickness.

Send the plan to the fab's CAM group and get a pressed-thickness drawing back before the artwork is frozen. If the fab cannot hold the dielectric heights the impedance depends on, that is a stackup change, and it is far cheaper before routing than after.

Our DFM/DFA layout service work includes that conversation with the board shop, so the stackup in the fabrication notes is the one that gets built.

FAQ

Common questions

Start from routing demand, interface count and reference-plane requirements, then confirm with cost. A useful first estimate is the quote tool's suggested stackup from your component, pin and net counts. The planner takes that count and checks that it can actually be built with continuous references and reachable impedances; it does not pick the count for you.

Keep going

Impedance calculator Via stub resonance DDR length matching Layout cost estimator SI/PI verification service published layout pricing

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