SI/PI simulation or DRC: how much analysis the board actually needs
Simulation is not a virtue in itself. A four-layer control board routed to good rules does not need S-parameter extraction, and a 112G channel will not pass on rules of thumb. The decision comes down to margin: how much of the channel budget is left after the fixed losses, and what a respin would cost.
What DRC proves
What a rule check can and cannot tell you
DRC proves that the layout matches the rule deck. If the deck encodes the right impedance, spacing, length windows and reference requirements, a clean report means the board was routed to the constraints you chose. That is a real result, and for many boards it is sufficient.
What DRC cannot do is tell you whether the constraints were right. It does not model frequency-dependent loss, connector parasitics, plane resonances or the effect of a stub. It cannot tell you that a 6 dB margin at 16 GHz became 2 dB once the connector was added.
Decision
When extraction earns its cost
Add simulation when the margin is thin or the cost of being wrong is high. In practice that means the following cases.
- Serial lanes at 16 GT/s and above, where the board's share of the loss budget is a few decibels.
- Long channels: backplanes, cables, risers, or anything with two connectors in series.
- Stackups that are unusual for the team: very thin dielectrics, mixed laminates, or HDI builds with multiple sequential cycles.
- Power delivery where the load steps are large and the core voltage is below 1 V, so IR drop is not the question and transient droop is.
- Any design where a respin costs more than the analysis: long-lead fabrication, expensive assemblies, or a schedule with no slack.
- A first board from a team that has not routed this interface before, even at a modest rate.
When the answer is yes, the scope is on our SI/PI verification service page, and the routing rules that come out of it are applied on the high-speed PCB layout service page.
Deliverable
What a sign-off dossier contains
An eye-diagram screenshot is not a deliverable. A dossier is an auditable record: which models were used and at what revision, which stackup and material properties were assumed, the extracted S-parameters, the compliance mask the result was compared against, and the margin at the target bit error rate.
It also has to say what was not verified. Every model has limits, and a dossier that does not name them is asking the reader to assume there are none. If the connector model was supplied by the vendor at a nominal impedance, or the package model was unavailable, that belongs on the first page.
- Model versions: IBIS, IBIS-AMI and any vendor S-parameter files, with revisions
- Stackup and material assumptions, including Dk and Df at the frequencies used
- Extracted channel data as Touchstone files for the routed geometry
- Insertion and return loss plotted against the applicable compliance mask
- Eye width and height at the specified BER, with the margin stated in numbers
- PDN impedance against frequency, with the target impedance marked
- Documented exceptions and the assumptions behind each one
For geometry work before extraction, the Impedance calculator and Via stub resonance calculators cover the closed-form cases; the SI/PI verification service page covers the field-solver work.
FAQ
Common questions
Want this worked through on your board?
Send the stackup and interface list and we will check the SI/PI scope against a real layout — before the quote is fixed, not after.