Do I match DDR trace lengths or propagation delays?

Delays. Length is only a convenient proxy when every net is on the same layer with the same effective Dk. A microstrip segment and a stripline segment of the same length arrive at different times, so a mixed-layer route has to be matched in time and then converted back to length per layer.

Should DQ be matched to DQS or to the clock?

DQ is sampled by its byte-lane DQS, so the primary constraint is DQ-to-DQS within the lane. The address and command bus is captured by the clock, so it is matched to CK. The clock pair itself is an intra-pair constraint. These are separate groups and the calculator reports them separately.

Is this calculator a JEDEC compliance check?

No. It converts a skew allowance into a routing window. JEDEC timing parameters describe the silicon's sampling requirements; the controller and DRAM vendor guidance turns those into board constraints. The default fractions are planning values, clearly labelled as such, and must be replaced with your datasheet numbers.

How do package delays and fly-by topology fit in?

Package delay is a static term in the budget. In a fly-by topology, the clock or command signal reaches each DRAM at a different time, so the per-load segments are matched to the topology rather than to one end-to-end number. The calculator gives the per-group window; the topology decides how it is distributed across loads.

Why did the result change when I switched from stripline to microstrip?

Microstrip has part of its field in air, so its effective Dk is lower and its propagation delay is smaller. The same time window therefore corresponds to a longer physical trace. The calculator shows both delays and the equivalent-length factor so the difference is visible rather than buried in a constant.

Free tool · DDR timing

DDR length-matching budget: turn a skew allowance into a length window

Enter the data rate, stackup and fixed skew terms to get the maximum length mismatch for every DDR match group — in picoseconds, millimetres and mils — before a single trace is routed.

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The short answer

The length window is the allowed skew in time divided by the propagation delay per millimetre. At 3200 MT/s one UI is 312.5 ps; a 2% DQ-to-DQS allowance is 6.25 ps, which is about 0.90 mm (36 mil) on an inner FR-4 layer. Subtract the package, weave and via terms you cannot tune out first — the remainder is what the router may spend.

Calculator

DDR length-matching calculator

Every field validates as you type. Change the data rate, the stackup or a fixed term and the per-group windows update immediately; a group that has no budget left is marked rather than silently returning a negative length.

Data-rate preset (arithmetic only — no JEDEC timings implied)

Data rateMT/s

The MT/s figure from the part number — not the clock frequency.

Laminate Dk (25 °C)

Routing layer

Operating temperature°C

Dk temperature coefficientppm/°C

0 disables the correction; take the value from the laminate datasheet.

Match-group allowances

Percent of one UI. Replace the planning defaults with your controller or DRAM vendor numbers.

DQS± intra-pair

DQ ↔ DQS within a byte lane

Byte lane ↔ byte lane

Address / command ↔ CK

CK ↔ CK# intra-pair

Fixed implementation terms

Static skew the router cannot tune out. Package mismatch is excluded from the differential pairs; weave and via asymmetry apply to both scopes.

Package / device mismatch

Connector or DIMM pin skew

Fiber-weave / Dk variation

Via and layer-change asymmetry

Other fixed allowance

Budget at the receiver

One UI, the effective delay and the fixed terms that consume the allowance.

Within budget

Unit interval: 312.50ps
Nyquist: 1.600GHz
Dk at temperature: 4.3000
Delay: 6.917ps/mm
One UI of length: 45.179mm
Thermal drift: 0.0000ps/mm
MS → SL length factor: 0.874
Fixed terms (between): 2.50ps

All match groups have a length window

Every group has a positive net allowance after the fixed terms. Hand the per-group windows to the router with a layer column, then verify the actual lengths in time rather than in millimetres.

Per-group length windows

Gross allowance, the fixed terms that consume it, and what is left for copper — in picoseconds, millimetres and mils.

DDR match-group length budgets, in picoseconds, millimetres and mils.
Group	Gross ps	Fixed ps	Net ps	Window mm	Window mil	Status
DQS± intra-pair	4.69	1.50	3.19	0.461	18.1	OK
DQ ↔ DQS within a byte lane	6.25	2.50	3.75	0.542	21.3	OK
Byte lane ↔ byte lane	15.63	2.50	13.13	1.898	74.7	OK
Address / command ↔ CK	6.25	2.50	3.75	0.542	21.3	OK
CK ↔ CK# intra-pair	4.69	1.50	3.19	0.461	18.1	OK

A window is the maximum spread within the group, not a target length. Centre the target and the allowed difference is twice the quoted number.

Layer-change converter

Equal lengths on microstrip and stripline are not equal times. Convert a segment before adding or removing copper.

Length to convertmm

From

43.723 mm of stripline is time-equal to 50.000 mm of microstrip.

That is 1,721.4 mil, with a length factor of 0.874.

What this budget does not know

It does not know your topology, package lengths, ODT settings, receiver equalisation or the exact JEDEC timing table for your part. The default fractions are planning values, not limits. Use the number as a routing target, then verify the interface in a channel simulation before sign-off.

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Free, no account. The engineer reviews the inputs before a fixed quote is issued.

Want the derivation? Jump to the math behind the calculator.

The math

The formulas, with the working shown

Each equation is rendered as MathML, explained in plain language, and shown as LaTeX source you can copy. The variable list says what every symbol means; the model-limit note says where the formula stops being trustworthy.

The unit interval

U I_{p s} = \frac{10^{6}}{f_{data}}

One UI is the time between two consecutive bits on a data pin. DDR transfers on both clock edges, so the data rate in MT/s already counts both — do not halve it again.

UI: unit interval, the bit time at the receiver
f_data: data rate in MT/s (megatransfers per second)

A data rate is quoted in megatransfers per second (MT/s), not in clock frequency. At 3200 MT/s the receiver sees a new bit every 312.5 ps, whether the clock itself is 1600 MHz or not.

Everything else on this page is expressed as a fraction of this number. That is why a design can pass at DDR4-2400 and fail at DDR4-3200 with exactly the same layout: the copper did not change, but the UI it has to fit inside did.

Model limit: At 3200 MT/s: UI = 10^6 / 3200 = 312.5 ps. At 6400 MT/s: 156.25 ps. The window halves when the rate doubles.

LaTeX source

UI_{ps} = \frac{10^6}{f_{\text{data}}}

Propagation delay per millimetre

t_{p d} = \frac{\sqrt{ε_{e f f}}}{c_{0}} \Rightarrow t_{p d} [\frac{ps}{mm}] = 3.3356 \sqrt{ε_{e f f}}

The speed of an edge on a PCB trace is set by the effective permittivity of the material around it. The constant 3.3356 is simply 1/c0 expressed in picoseconds per millimetre.

c0: speed of light in vacuum (299,792,458 m/s)
ε_eff: effective relative permittivity of the line
t_pd: delay per unit length, usually ps/mm

Light in vacuum travels 299.792 mm in one nanosecond, which is 3.3356 ps per millimetre. The laminate slows it by the square root of the effective Dk, so a trace in FR-4 with εeff = 4.3 runs at about 6.9 ps/mm.

This is the conversion factor between the time budget and the length budget. Every length figure in the calculator is the net time divided by this number, which is why the layer type matters: microstrip and stripline have different εeff.

Model limit: εeff = 4.3 gives 6.92 ps/mm; εeff = 3.3 gives 6.06 ps/mm. Over a 300 mm channel that is a 258 ps difference — comparable to a whole DDR5 UI.

LaTeX source

t_{pd} = \frac{\sqrt{\varepsilon_{eff}}}{c_0} \quad\Rightarrow\quad t_{pd}\left[\frac{\text{ps}}{\text{mm}}\right] = 3.3356\sqrt{\varepsilon_{eff}}

Effective Dk of a microstrip line

ε_{e f f} = \frac{ε_{r} + 1}{2} + \frac{ε_{r} - 1}{2} {(1 + \frac{10 h}{w})}^{- a b}

A microstrip line is half in laminate and half in air (or soldermask and air), so its effective Dk is between 1 and the laminate Dk. Wider traces push more of the field into the laminate and raise εeff toward εr.

ε_r: relative permittivity (Dk) of the laminate at the design frequency
h: dielectric height from the trace to its reference plane
w: trace width (the effective width includes copper thickness)
a, b: the empirical correction exponents in the next block

The first term is the air/laminate average; the second term is the correction that makes a narrow trace behave more like air and a wide trace behave more like the laminate. The exponents a and b are empirical fits from Hammerstad and Jensen, given in the next block.

There is no such ambiguity for stripline: the field is entirely inside the laminate, so εeff equals εr exactly. That is why an inner-layer trace is slower than an outer-layer trace of the same length.

Model limit: The page uses this model to convert a microstrip length into time. It is a quasi-static fit: dispersion above a few GHz and the soldermask are not included.

LaTeX source

\varepsilon_{eff} = \frac{\varepsilon_r+1}{2} + \frac{\varepsilon_r-1}{2}\left(1+\frac{10h}{w}\right)^{-ab}

The Hammerstad–Jensen exponents

a = 1 + \frac{1}{49} \ln (\frac{u^{4} + (u / 52)^{2}}{u^{4} + 0.432}) + \frac{1}{18.7} \ln (1 + {(\frac{u}{18.1})}^{3}) b = 0.564 {(\frac{ε_{r} - 0.9}{ε_{r} + 3})}^{0.053}

These are the fitted terms behind the effective-Dk equation. They are why the calculator can be trusted to a few percent without a field solver for ordinary FR-4 geometries.

u: w/h, the width-to-height ratio
ln: natural logarithm

u is the width-to-height ratio w/h. As u grows, a tends toward 1 and the second term vanishes, so the equation collapses toward εeff → εr. As u shrinks, the correction becomes stronger and εeff falls toward (εr+1)/2.

The constants are not adjustable: they come from the published fit. Changing them would make this calculator disagree with the impedance tool on the same geometry, which is exactly the kind of drift the shared model prevents.

Model limit: The fit is quoted as accurate to about 1% for 0.1 ≤ w/h ≤ 10 and 1 ≤ εr ≤ 15 with t ≤ 0.2h.

LaTeX source

a = 1 + \frac{1}{49}\ln\left(\frac{u^4+(u/52)^2}{u^4+0.432}\right) + \frac{1}{18.7}\ln\left(1+\left(\frac{u}{18.1}\right)^3\right) \quad b = 0.564\left(\frac{\varepsilon_r-0.9}{\varepsilon_r+3}\right)^{0.053}

The net routing budget

t_{net} = k U I - \sum_{i} t_{fixed, i}

The router only gets what the fixed implementation terms leave behind. k is the fraction of a UI the interface allows for skew; the sum is every static term you cannot tune out with copper.

k: allowed skew as a fraction of one UI (the group's percentage divided by 100)
t_fixed,i: a static term such as package mismatch or fibre-weave skew, in ps

This subtraction is the heart of the calculator. If the interface allows 5% of UI but the package, connector, weave and via terms already consume 4%, the router has 1% of UI to work with — not 5%.

The calculator applies each fixed term only to the groups it can affect. Package mismatch is common-mode inside a differential pair, so it is excluded from the intra-pair budget; weave and via asymmetry are not.

If t_net is zero or negative the group is reported as over budget. The length is not clamped to zero and presented as valid — there is no honest length window to give.

Model limit: A group marked tight has less than a quarter of its gross allowance left; that is a warning to revisit the stackup or the fixed terms, not a pass.

LaTeX source

t_{\text{net}} = k\,UI - \sum_{i} t_{\text{fixed},i}

From time to copper

Δ L = \frac{t_{net}}{t_{p d}} Δ L_{mil} = \frac{Δ L_{mm}}{0.0254}

Divide the net time by the delay per millimetre and the budget becomes a routing number. The result is a worst-case difference, not a target length.

ΔL: allowed length difference within the group
t_net: the net time budget from the previous block
t_pd: delay per millimetre for the layer the group runs on

A window of ±0.45 mm means the shortest and longest net in the group may differ by 0.45 mm in time-equivalent length. It does not mean every net must be 0.45 mm longer than some arbitrary reference.

The calculator reports millimetres and mils side by side because the two conventions are both in use. One mil is 0.0254 mm, so 1 mm is 39.37 mil.

When the group contains both microstrip and stripline segments, convert each segment to time first and add the times — never add the physical lengths and divide once.

Model limit: The figure is a maximum spread. A ±0.45 mm window is 0.90 mm end to end if the router centres the target.

LaTeX source

\Delta L = \frac{t_{\text{net}}}{t_{pd}} \quad\quad \Delta L_{\text{mil}} = \frac{\Delta L_{\text{mm}}}{0.0254}

Temperature moves the window

ε_{r} (T) = ε_{r} (25) [1 + α_{Dk} (T - 25)] Δ t_{p d} = 3.3356 (\sqrt{ε_{r} (T)} - \sqrt{ε_{r} (25)})

Laminate Dk rises with temperature for most FR-4 materials, which slows every trace. The effect is small per millimetre but it accumulates over a long channel and is not symmetric between layers.

α_Dk: Dk temperature coefficient, ppm/°C
T: operating temperature, °C
Δt_pd: change in propagation delay per millimetre

α_Dk is quoted by the laminate manufacturer, usually in ppm/°C. A positive coefficient means a hotter board has a higher Dk, a slower edge and a longer electrical length.

The calculator reports the drift in ps/mm between 25 °C and the temperature you enter. Multiply by the channel length to see whether the window survives the operating range.

The default is zero because a generic coefficient would be a guess. Enter the number from the laminate datasheet, or leave it at zero and treat the result as a room-temperature budget.

Model limit: A +200 ppm/°C laminate at 85 °C raises Dk by about 1.2%, which raises delay by about 0.6%. Over 300 mm that is roughly 12 ps — a real fraction of a DDR5 UI.

LaTeX source

\varepsilon_r(T) = \varepsilon_r(25)\left[1+\alpha_{\text{Dk}}(T-25)\right] \quad\quad \Delta t_{pd} = 3.3356\left(\sqrt{\varepsilon_r(T)}-\sqrt{\varepsilon_r(25)}\right)

Equivalent length across a layer change

L_{stripline} = L_{microstrip} \frac{t_{p d, microstrip}}{t_{p d, stripline}}

When a net changes layer, convert the existing length into the delay of the new layer before adding or removing copper. Equal physical lengths on different layers are not equal times.

L_microstrip: physical length of the outer-layer segment
t_pd,microstrip: microstrip delay per millimetre
t_pd,stripline: stripline delay per millimetre

The ratio is always less than one when moving from microstrip to stripline, because stripline is slower. A 50 mm microstrip segment is about 40.6 mm of stripline for the same delay in the worked example on this page.

The converter in the calculator uses the same effective-Dk model as the rest of the page. If the microstrip geometry is missing, it falls back to the laminate Dk, which overstates the microstrip delay and therefore the correction.

Via stubs add a frequency-dependent discontinuity that this linear conversion cannot capture. Check the stub separately when the channel is above a few GHz.

Model limit: This is a time-equivalence correction, not an impedance correction. A layer change also needs a via and a return-path check.

LaTeX source

L_{\text{stripline}} = L_{\text{microstrip}}\frac{t_{pd,\text{microstrip}}}{t_{pd,\text{stripline}}}

Source-synchronous timing

From a unit interval to a length window

DDR data is source-synchronous: DQ travels alongside a differential strobe, DQS, and the receiver samples on the strobe's crossing rather than against a system clock. The constraint is therefore a time window, not a length. Length is only how that window gets expressed to a router.

Divide the allowed skew by the propagation delay per unit length and you have the window: ΔL = Δt / t_pd. The catch is that t_pd is not constant. An inner stripline in FR-4 runs near 6.1 ps/mm; an outer microstrip is faster because half its field is in air. A byte lane that changes layers cannot be matched by total length — it has to be matched by delay.

On boards that carry memory and a fast serial interface together, the high-speed PCB layout service engagement sets both constraint sets before routing starts.

Match groups follow the interface: DQ to DQS within a byte lane, the DQS pair to itself, CA and clock as their own group.
The allowance is a fraction of the unit interval defined by the DRAM and controller, not a house rule.
Fixed terms — package skew, connector pin fields, layer-transition delay — come off the top before the router gets anything.
A group with no budget left means the stackup, rate or package allocation has to change. The tool says so instead of returning a negative length.

DDR match groups, the timing parameter each one controls, and what fails when it is exceeded.
Match group	What it controls	Failure mode
DQS+ / DQS− pair	Crossing alignment and duty cycle	Phase jitter, duty-cycle distortion, sampling window collapse
DQ ↔ DQS in a byte lane	Setup and hold relative to the strobe	Read or write errors in one lane; training failure
Byte lane ↔ byte lane	Arrival spread across lanes	Longer controller training, cross-lane synchronisation stalls
Address/command ↔ CK	Command latching against the clock	Command parity errors, erratic initialisation over temperature

Each group is an independent constraint and cannot be pooled. The Impedance calculator gives the propagation delay for the geometry you are about to route.

CAD implementation

Putting the budget into the constraint manager

Enter the controller and DRAM package delays into the fixed terms before routing starts. Package skew is not something a router can tune out, and a constraint set that ignores it will approve a byte lane that is already over budget.

When a lane changes layers, account for the velocity step. Handing a router a physical-length rule across a microstrip-to-stripline transition produces a time-domain skew the length report will call matched. A report that only measures length is measuring the wrong thing.

Use the laminate Dk at the operating frequency, and the effective Dk for microstrip.
Allow for the positive thermal coefficient of Dk if the board runs hot.
Tighten the DQS pair first, then the intra-lane DQ bits.
Convert length to delay at each layer transition, not once at the end.

Symmetric dielectric heights make the length rules portable between layers; the Stackup planner models that symmetry directly.

Honesty about the numbers

What the defaults mean — and what they do not

The five fraction-of-UI defaults and the fixed terms are planning values chosen to produce a sane starting point across DDR3, DDR4 and DDR5. They are not JEDEC limits, they are not a compliance statement, and they are not a substitute for the timing table in the controller datasheet. Replace them with your own numbers before you hand a constraint set to a router.

The distinction matters because a JEDEC timing parameter such as tDS or tDH describes the silicon's sampling requirement; the layout budget is the slice of that requirement left for copper after package, clocking and channel effects. Treating a percentage of UI as a JEDEC number is how boards get routed to a window that was never real.

For a board where this budget is tight, the useful next step is not a longer serpentine. It is a stackup with thinner dielectric, a via strategy that removes stubs, and a simulation of the actual channel. Our SI/PI verification service exists for that step, and the published layout pricing page shows what a fixed-fee engagement includes.

The calculator cannot see topology, package lengths, ODT settings or the receiver's equalisation. It gives a defensible routing window; it does not sign the interface off.

The trap

Equal length is not equal time

A microstrip trace on the outer layer has part of its field in air, so its effective Dk is lower and it is faster than a stripline trace of the same physical length. Move a byte lane from an outer layer to an inner layer and the length report can look perfect while the timing is not. The calculator reports delay per millimetre for both layer types and converts one into the other.

The correction is not a fudge factor; it is the ratio of the two propagation delays. If the microstrip delay is 5.6 ps/mm and the stripline delay is 6.9 ps/mm, then 50 mm of microstrip is time-equal to about 40.6 mm of stripline. Add the 40.6 mm, not 50 mm.

Layer changes also introduce via stubs, which are a frequency-dependent discontinuity rather than a simple delay. The Via stub resonance checks whether the stub resonates inside the channel, and the Impedance calculator gives the impedance and delay of each line type.

FAQ

Common questions

It depends on the interface generation, the data rate and the controller vendor's guidance. As a planning example, at DDR4-3200 a 2% of UI DQ-to-DQS allowance is 6.25 ps; on an inner FR-4 layer that is about 0.90 mm (36 mil) before fixed terms are subtracted. At DDR5-4800 the same 2% is 4.17 ps, about 0.60 mm (24 mil). Enter your own allowance and fixed terms in the calculator rather than using these as limits.

Keep going

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