DDR5 layout guidelines: subchannels, skew and the budget you actually have
DDR5 changes the routing problem before it changes the rules. Each DIMM or package splits into two independent 32-bit subchannels, the data rate runs from 4800 to 8800 MT/s, and a decision-feedback equalizer inside the DRAM is doing work that used to be the layout's job. Match what the controller asks for, not a number copied from a DDR4 board.
Topology
Two subchannels change the topology
A DDR5 channel is two 32-bit subchannels, each with its own address and command bus, clock pair and data lanes. That halves the load on any single bus compared with a 64-bit DDR4 channel and makes point-to-point routing the normal case for a single rank. It also means a byte-lane mistake affects a smaller share of the bus, which is a poor reason to relax: a failing subchannel fails training.
The address, command and control bus is still a multi-drop bus when more than one rank shares it, and it is still referenced to the clock. Fly-by remains the right topology on a DIMM; on a discrete down-board layout the bus is usually short enough that a simple daisy chain with controlled stubs meets the controller's window.
- Route each subchannel as its own bus: separate CA, clock and DQ groups per subchannel.
- Keep the clock pair referenced to a continuous plane for the whole run, including under the DIMM connector.
- Match CA and clock within the controller's window, not against a rule of thumb.
- Treat the DQS pair as the reference for its byte lane and match DQ to it after the pair itself is matched.
Timing budget
Build the skew budget before you route
At 4800 MT/s one unit interval is 208 ps. The controller datasheet gives you a fraction of that — often 2 to 5 percent — as the total allowable DQ-to-DQS skew. That number is not the routing budget. Subtract package skew between the controller and the DRAM, connector pin-field skew, and the time added by layer transitions, and what is left is the window the router can spend.
Convert it to length only after the layer stackup is fixed. On a 100 µm prepreg with Dk around 4.0, propagation is roughly 6.1 ps/mm on an inner layer and faster on the outer microstrip. A byte lane that changes layers twice needs its delay computed per segment, not its total length matched.
| Budget term | Typical source | Can layout recover it? |
|---|---|---|
| Controller package skew | Controller datasheet | No — deduct it up front |
| DRAM package skew | DRAM datasheet | No — deduct it up front |
| Connector pin-field skew | Connector footprint geometry | Partly, by pin assignment and escape |
| Via and layer-transition delay | Stackup, via depth | Yes — compensate in trace length |
| Intra-pair DQS skew | Routing discipline | Yes — tune the pair first |
| Trace length mismatch | Router | Yes — this is the remainder |
The DDR length matching turns the allowance into per-group length windows and subtracts the fixed terms; the Impedance calculator gives the propagation delay for the geometry you are about to route.
Power and reference
VDDQ, the PMIC and why the reference plane is not optional
DDR5 moves the DIMM power management onto the module: the PMIC sits on the DIMM and generates VDD, VDDQ and VPP from 12 V. On a discrete layout, that means a switching regulator close to the DRAM, and switching noise is now a memory-layout problem. Keep the inductor and its switching node away from the DQS pairs and the clock; do not route a data lane across the gap in the ground plane under the regulator.
VDDQ is 1.1 V and the data signals are terminated on-die, so there is no external VTT rail to route. The return path still has to be continuous. Every DQ and DQS trace should see an uninterrupted reference plane from the controller pin to the DRAM ball, and that plane should be stitched to the ground plane with vias around the DRAM field.
Sign-off
What to check before you release the board
- Every match group reports measured skew against its window, per segment, not per net length.
- No DQ or DQS net crosses a plane split; trace the reference layer on every layer transition.
- DQS pairs are routed with symmetric via counts and matched pair lengths before intra-lane tuning.
- CA and clock are matched as their own group, with the clock pair's reference continuous through the connector.
- Decoupling is placed against the DRAM and controller power pins with the via-to-pad path kept as short as the fanout allows.
- Test access exists for bring-up: probe points on the clock and at least one DQS pair per subchannel.
Where the channel budget is tight, post-route extraction on our SI/PI verification service page turns these checks into measured numbers instead of routing intent.
FAQ
Common questions
Want this worked through on your board?
Send the stackup and interface list and we will check the DDR5 channel against a real layout — before the quote is fixed, not after.