What to send a layout engineer on day one
Most layout delays start with the handoff, not the routing. A complete package takes an afternoon to assemble and saves a week of questions. Here is the list we ask for, and the cost of leaving each item out.
The package
The six items that make a handoff complete
Everything below is something the layout depends on. If an item is genuinely undecided, say so and mark it as an assumption; an open question is manageable, a silent gap is not.
| Input | What good looks like | Cost of leaving it out |
|---|---|---|
| Schematic and netlist | Native Altium project, or an export with a complete netlist | Connectivity ambiguity; nets get guessed and rework follows |
| Mechanical outline | Dimensioned DXF plus a 3D STEP of the enclosure and mating parts | Connector or height collisions found after routing |
| BOM | Current BOM with reference designators and manufacturer part numbers | Footprint guesses, wrong pad geometry, assembly defects |
| Constraints | Impedance targets, length windows, current, isolation and thermal limits | Rules invented by the layout engineer instead of taken from your design |
| Stackup and fab data | Preferred layer count, materials, finish, or the fab's own stackup | A board that has to be re-impedanced after the quote |
| Interface list | Interface names, target speeds and the controller or PHY part numbers | Constraint set built on a guess about which bus is fast |
Constraints
What a usable constraint is
A constraint the layout can act on has a number, a net class and a source. "Keep DDR short" is not a constraint; a 6.25 ps DQ-to-DQS allowance applied to each byte lane, taken from the controller datasheet, is.
Where the datasheet gives a fraction of the unit interval, hand over the fraction and the data rate and let the length window be computed. Where the vendor supplies a layout guide, send it: it usually contains the exceptions that matter more than the general rule.
- Impedance targets per net class, with the stackup they assume
- Length and skew windows per match group, and the fixed terms to deduct
- Current and voltage isolation requirements, including creepage where relevant
- Thermal limits for power components and the ambient they see
- Any net, part or area that must not move, and why
The DDR length matching turns a timing allowance into length windows you can put straight into a constraint manager.
Pitfalls
Four habits that stall a layout
These are the ones we see most often, and each one costs days rather than hours.
- Sending a 2D outline without 3D models for tall or custom parts, then discovering the collision at the first review.
- Updating the schematic mid-placement without an ECO summary, so the netlist and the board drift apart.
- Leaving the stackup to the layout engineer when the fab has already quoted a different one.
- Withholding the vendor's layout guide for a processor or PHY because it is long; the escape and via rules in it are usually the difference between working and marginal.
Our our onboarding process covers the same inputs from the commercial side, including when the NDA has to be signed relative to the file transfer.
FAQ
Common questions
Want this worked through on your board?
Send the stackup and interface list and we will check the layout handoff against a real layout — before the quote is fixed, not after.