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Turn a rail's ripple and load step into a target impedance, then sweep a real capacitor bank against it and find the anti-resonance that adding more parts makes worse.
The short answer
A power distribution network holds a rail steady by keeping its impedance below a target at every frequency the load draws current. The target is the allowed ripple voltage divided by the load step: a 0.9 V rail with 3% ripple and a 20 A step needs 1.35 milliohms. A capacitor meets that at low frequency, but its own equivalent series inductance turns it into an inductor above self-resonance, so a bank is judged across a sweep — and two different parts in parallel produce a peak between their resonances that more of either one cannot fix.
Calculator
Enter the rail, the ripple and the load step to get the target impedance, then describe two capacitor types and the plane pair. The sweep sums the parts' admittances — each modelled as ESR + jωL + 1/(jωC) — and reports the worst impedance, the frequency where the bank stops meeting the target, and the anti-resonance between the two parts. The plane-pair capacitance and its first cavity mode are shown as context, not folded into the bank.
Rail and load step
Plane pair and sweep
Ceramic part
Bulk part
Bank impedance against the target
Admittances summed, self-resonance included, anti-resonance named.
Worst impedance 571.8 milliohms against a 1.4 milliohm target.
3.0% of 0.90 V over 20 A.
At 4 MHz.
571.8 mΩ peak.
Last frequency under target before the first violation.
First cavity mode 808 MHz.
0.7 MHz / 22.5 MHz self-resonance.
Sweep
| Frequency MHz | |Z| mΩ | Target mΩ | Status |
|---|---|---|---|
| 0.1 | 75.10 | 1.4 | Over |
| 0.3 | 23.22 | 1.4 | Over |
| 0.8 | 3.48 | 1.4 | Over |
| 2.2 | 48.60 | 1.4 | Over |
| 6.3 | 42.08 | 1.4 | Over |
| 17.6 | 5.13 | 1.4 | Over |
| 49.5 | 15.33 | 1.4 | Over |
| 139.3 | 52.06 | 1.4 | Over |
Model notes
Where this model stops
Free, no account. The engineer reviews the inputs before a fixed quote is issued.
Want the derivation? Jump to the math behind the calculator.
The math
Each equation is rendered with KaTeX, which also emits a MathML twin for screen readers and answer engines, explained in plain language, and copyable as LaTeX from the button in its corner. The variable list says what every symbol means; the model-limit note says where the formula stops being trustworthy.
The network must hold this impedance from DC to the highest frequency the load draws current at.
The rail voltage times the allowed ripple fraction is the voltage disturbance the load tolerates; dividing by the current step turns it into an impedance.
A 0.9 V rail with 3% ripple and a 20 A step gives 1.35 mΩ. Halving the ripple halves the target, and the bank has to be twice as good everywhere.
Model limits
This uses the full transient. Some references halve the step for a symmetric load change, which doubles the target; the conservative form is used here.
A capacitor is a resonant circuit: capacitive below self-resonance, inductive above it, and its ESR at the crossing.
Below resonance the capacitive term dominates and impedance falls with frequency. Above it the inductive term wins and impedance rises, which is why a part stops helping.
At self-resonance the two reactances cancel and the impedance is exactly the ESR, which is why low-ESR parts are specified for the high-frequency end of a bank.
Model limits
The model is a series RLC with constant values. Dielectric absorption, DC bias derating and temperature are not included, and X5R ceramics lose much of their capacitance under bias.
The frequency at which a part stops behaving as a capacitor.
A 0.1 µF ceramic with 0.5 nH of ESL resonates near 22 MHz. A 10 µF bulk part with 5 nH resonates near 0.7 MHz.
The gap between those two resonances is where the anti-resonance lives, which is why a bank's worst impedance is often at a frequency no single part was chosen for.
Model limits
Mounting inductance usually exceeds the part's own ESL, and it is set by the via pair and the pad geometry rather than by the capacitor's datasheet.
Admittances add, so the bank is the parallel combination of complex impedances, not the sum of capacitances.
Each part contributes its admittance, multiplied by how many are placed. The reciprocal of the sum is the bank impedance.
This is what makes the anti-resonance appear even though every individual part is well behaved: at the peak, the inductive admittances of the bulk parts cancel the capacitive admittances of the ceramics.
Model limits
The model assumes the parts share current equally, which stops being true as the copper between them and the load starts to matter.
Target
The load draws a current step in a few nanoseconds, and the network has to supply it before the regulator can respond. The allowed voltage disturbance divided by that step is the impedance the network must hold: a bigger step or a tighter ripple makes the target harder, and the capacitance needed follows from it.
That is why adding capacitance without a target is not a design: a bank can meet 20 milliohms easily and miss 1 milliohm everywhere, and the answer depends on the frequency range the load actually draws at.
Anti-resonance
Take a 10 µF bulk part and a 0.1 µF ceramic. At a few megahertz the bulk part has turned inductive and the ceramic is still capacitive, so the two form a parallel resonant circuit: the inductance of one rings against the capacitance of the other, and the impedance peaks between them.
Adding more of either part lowers the impedance outside that peak and leaves the peak where it is — sometimes higher, because there is more of the reactance that causes it. The fix is a part whose self-resonance falls inside the gap, or enough ESR to damp the peak.
On a real board the spreading inductance of the planes and the package's own PDN sit on top of this. That network, with the cavity modes, is the SI/PI verification service engagement.
FAQ
Send the stackup and interface list. We will check the decoupling network against the real layout before the quote is fixed.